High resolution phase frequency detectors

ABSTRACT

An inexpensive and reliable, high resolution digital phase detector for timing circuits for wireless, optical or wire-line transmission systems. In particular this invention allows using size limited clock counters for measurements of unlimited time ranges by combining unlimited number of intermediate samples without accumulating samples granularity errors. In addition to the measurements of the final time ranges, the intermediate samples are available for purposes of digital signal processing.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention is directed to providing high resolution low costdigital phase detectors which can be used in digital phase locked loops(DPLLs) and shall also make possible other replacements of analogcircuits by their digital implementations.

[0003] The high resolution phase detectors (HRPD) can be used for a widerange of data rates, and for wireless, optical, or wireline transmissionand communication systems.

[0004] 2. Background Art

[0005] Most of currently used digital phase detectors have resolutionlimited by a clock cycle time.

[0006] While some most advanced digital phase detectors allow higherresolutions which are comparable with propagation delays of clockpropagating gates, they have other limitations such as: complexalgorithms which are conditioned by propagation delays of detectortiming circuits, and dependency of their phase resolution ontechnological process and power supply variations.

[0007] There is a need for digital phase detectors which have simpleralgorithms and greater independence versus the propagation delays of thedetector timing circuits and the clock propagating gates.

SUMMARY OF THE INVENTION

[0008] 1. Purpose of the Invention

[0009] It is an object of present invention to provide digital highresolution phase detectors which are simple and reliable and can be usedin variety of communication systems.

[0010] 2. General Description of the Invention

[0011] Variety of the high resolution phase detectors are described inthis document using the same terms which are explained below.

[0012] First signal clock f_(F1) is a higher frequency signal which isused to measure time periods corresponding to single or multiple cyclesof a lower frequency signal which is called second signal frame fr_(S2).

[0013] High resolution phase detectors comprise:

[0014] a counter and a buffer configuration for counting the firstsignal clock during every frame of a second signal, and for bufferingthe counted value until it is read by a phase processing unit;

[0015] a high resolution extension of the counter and bufferconfiguration, which measures a remainder of a frame phase skew which islesser than one clock cycle;

[0016] a detector timing circuit for synchronizing the clock countingand the buffer reading versus the signal frame related phase captureinto a phase capture register;

[0017] a high resolution phase processing method for combining contentsof the clock counter and the phase capture register into a highresolution phase measurement.

[0018] The high resolution extension can be implemented by using apropagation circuit and a phase capture register, as it is explainedbelow.

[0019] The first signal clock or the measured second signal frame ispropagated through multiple serially connected gates.

[0020] The first signal clock or the second signal frame is captured inthe phase capture register by the outputs of the serially connectedgates, or the outputs of the serially connected gates are captured inthe phase capture register by the first signal clock or by the secondsignal frame.

[0021] The content of the phase capture register is used to calculate aphase skew of the second signal frame versus the first signal clock.

[0022] The high resolution phase processing method comprises:

[0023] a calculation of an approximate phase error between the firstsignal and the second signal, by subtracting a number of first signalclock cycles which corresponds to zero phase skew of the second signalframe, from a last number of clock cycles which has been read from thebuffer;

[0024] a calculation of a high resolution phase error by adding the highresolution extension to the approximate phase error;

[0025] elimination of phase error accumulations for multiplemeasurements, by subtracting last high resolution extension from aperiod of the first signal clock, and by adding the resulting remainderof the clock cycle to an adjacent phase error measurement.

[0026] The above design principles and methods allow designing multipledifferent implementations of HRPD.

[0027] Some of these HRPD implementations are defined below and areshown with more details in the section DESCRIPTION OF THE PREFERREDEMBODIMENTS.

[0028] 3. HRPD Config.1 based on delay line captured by frame edge

[0029] The HRPD Config.1 uses:

[0030] an open ended delay line which is built with multiple seriallyconnected gates, which the first signal clock is continuously propagatedthrough;

[0031] a leading edge of the second signal frame to capture a status ofthe outputs of the delay line in the phase capture register;

[0032] a calibration method of gates propagation delays, which is basedon capturing the whole cycle of the first signal clock as it ispropagated along the delay line and dividing the first signal cycle timeby the number of gates which carried the whole cycle propagation.

[0033] The calibration method comprises:

[0034] statistical averaging of the calibration result, in order toeliminate most of a granularity error caused by capturing of the integergates number and to reduce an error caused by power supply ripple.

[0035] The calibration method can further comprise a reduction of anerror caused by an occurrence of different gate delays at the end versusthe front of the delay line:

[0036] by assigning higher weights to the cycle gate number, if capturedcycle propagating gates are located at the front of the delay line;

[0037] by using the weighted cycle gate numbers for the statisticalaveraging of the calibration result.

[0038] 4. HRPD Config.2 based on ring oscillator captured by frame edge.

[0039] The HRPD Config.2 uses:

[0040] the signal propagation circuit which is built with multipleserially connected gates forming a ring oscillator which is phase lockedto the first signal clock;

[0041] a leading edge of the second signal frame to capture a status ofthe outputs of the ring oscillator gates in the phase capture register.

[0042] Since the number of ring oscillator gates and the first signalclock period are known, calibration of gates propagation delay is notneeded for the HRPD Config.2.

[0043] 5. HRPD Config.3 based on clock signal captured by frame delayline edges.

[0044] The HRPD Config.3 uses:

[0045] the signal propagation circuit which is built with multipleserially connected gates forming an open ended delay line, which thesecond signal frame is continuously propagated through;

[0046] the outputs of the delay line gates to capture a waveform of thefirst signal clock, in the phase capture register;

[0047] a calibration method of gates propagation delays, which is basedon capturing the whole cycle of the first signal clock as it occursalong the inputs of the phase capture register, and dividing the firstsignal cycle time by the number of the delay line gates which outputscaptured the whole clock cycle.

[0048] The calibration method comprises:

[0049] statistical averaging of the calibration result, in order toeliminate most of a granularity error caused by having an integer numberof the capturing gates, and to reduce an error caused by power supplyripples.

[0050] The calibration method can fierier comprise a reduction of anerror caused by an occurrence of different gate delays at the end versusthe front of the delay line:

[0051] by assigning higher weights for the cycle capturing gate number,if the cycle capturing gates are located at the front of the delay line;

[0052] by using the weighted cycle gate numbers for the statisticalaveraging of the calibration result.

[0053] 6. HRPD Config.4 based on frame delay line captured by clocksignal.

[0054] The HRPD Config.4 uses:

[0055] the signal propagation circuit which is built with multipleserially connected gates forming an open ended delay line, which thesecond signal frame is continuously propagated through;

[0056] the outputs of the delay line gates are captured by rising edgesof the first signal clock in phase capture registers;

[0057] a calibration method of gates propagation delays which is basedon capturing the frame delay line by 2 consecutive first signal rises,and dividing the first signal cycle time by a difference between numbersof gate delays which were captured by the consecutive first signalrises.

[0058] The calibration method comprises:

[0059] statistical averaging of the calibration result, in order toeliminate most of a granularity error caused by capturing an integernumber of the delay line gates, and to reduce an error caused by powersupply ripples.

[0060] The calibration method can further comprise a reduction of anerror caused by an occurrence of different gate delays at the end versusthe front of the delay line:

[0061] by assigning higher weights to the cycle capturing gate number,if the cycle capturing gates are located at the front of the delay line;

[0062] by using the weighted cycle gate numbers for the statisticalaveraging of the calibration result

[0063] 7. HRPD Config.5 based on frame captured by clock delay line.

[0064] The HRPD Config.5 uses:

[0065] the signal propagation circuit which is built with multipleserially connected gates forming an open ended delay line, which thefirst signal clock is continuously propagated through;

[0066] the outputs of the delay line gates to capture a rise of thesecond signal frame in the phase capture register;

[0067] a calibration method of gates propagation delays which is basedon:

[0068] capturing a frame rising edge by two consecutive rising edges ofthe signal clock which occur simultaneously along the delay line;

[0069] and dividing the first signal cycle time by a number of delayline gates which existed between said clock edges when they capturedsimultaneously the frame rising edge in the capture register;

[0070] a capture synchronization method which prevents the nextpropagated clock edges from overwriting said captures of the frame riseby said two consecutive clock edges.

[0071] The calibration method comprises:

[0072] statistical averaging of the calibration result, in order toeliminate most of a granularity error caused by having an integer numberof the capturing gates, and to reduce an error caused by power supplyripples.

[0073] The calibration method can further comprise a reduction of anerror caused by an occurrence of different gate delays at the end versusthe front of the delay line:

[0074] by assigning higher weights to the cycle capturing gate number,if the cycle capturing gates are located at the front of the delay line.

[0075] by using the weighted cycle gate numbers for the statisticalaveraging of the calibration result

[0076] 8. HRPD Config.6 based on frame captured by ring oscillator.

[0077] The HRPD Config.6 uses:

[0078] outputs of the signal propagation circuit, which is built withmultiple serially connected gates forming a ring oscillator which isphase locked to the first signal clock;

[0079] the outputs of the ring oscillator gates to capture a rise of thesecond signal frame in the phase capture register;

[0080] a capture synchronization method which prevents next propagatedclock edges from overwriting said capture of the rise of the secondsignal frame.

[0081] Since the number of ring oscillator gates and the first signalclock period are known, calibration of gates propagation delay is notneeded for the HRPD Config.6.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0082] 1. HRPD Config.1 based on delay line captured by frame edge

[0083] The HRPD Config.1 is shown in FIG. 1.

[0084] Approximate phase measurements are explained below.

[0085] The HRPD Config.1 uses two symmetrical phase counters buffers A/B(PCBA/PCBB), which perform reverse functions during alternative A/Bcycles of the frame signal fr_(S2). During the A cycle, the PCBA countsthe number of incoming f_(F1) clocks, but during the following B cyclethe PCBA remains frozen until its content is read by a phase processingunit (PPU), and subsequently the PCBA is reset before the beginning ofthe next A cycle. Reversibly, the PCBB performs counting during the Bcycle and is read and reset during the following A cycle.

[0086] Such symmetrical PCBA/PCBB configuration allows much more timefor counters propagation by inhibiting counting long before the actualreading takes place.

[0087] Therefore, much higher frequencies of counted clocks are allowedfor the same IC technology.

[0088] Generally speaking the above concept of a digital phase detector,represents one of several possible HRPD solutions, which are based oncounting the first signal clock during every frame of the second signal;wherein the second signal frame contains a number of the second signalclocks.

[0089] The symmetrical twin pair PCBA/PCBB configuration:

[0090] allows higher counting speeds by eliminating all problems relatedto counters propagation delays.

[0091] allows measurements of fr_(S2) versus f_(F1) phase errors, with aresolution of a single f_(F1) period.

[0092] When fr_(S2) rise signals the end of the current phasemeasurement, counting of f_(F1) clock is inhibited and the countercontent remains frozen, until the next rise of the fr_(S2) signal whenthe counted clock is enabled again. The whole fr_(S2) cycle is a verylong freeze period, which is more than sufficient to accommodate; anykind of counter propagation, the counter transfer to the phaseprocessing unit, and the counter reset. During the freeze period a matecounter is kept enabled and provides measurement of fr_(S2) phase.

[0093] More detailed operations of the PCBA/PCBB configuration for bothalternatives STOPA=1 and STOPB=1, are further explained below.

[0094] When STOPA signal is active, HRPD circuits perform listed belowfunctions.

[0095] The PCBB counts all rising edges of f_(F1) clocks.

[0096] When PCBB(9) goes high, the PCBB generates SEL9 signal. The SEL9activates RD_REQ which initiates the PPU to read PCBA via CNTR(15:0).

[0097] The PPU calculates an approximate phase error of previous fr_(S2)versus f_(F1), by subtracting from the newly read PCB, the number N off_(F1) clocks which nominally should correspond to the frame fr_(S2).

[0098] When CTRB(14) goes high, the PCBB generates SEL14 signal. TheSEL14 activates RST_PCBA which initiates PCBA reset circuits after itscontent has been read by PPU.

[0099] When fr_(S2) rise occurs, PRESTOP_FF is set to 1 and invertsSTOPA/STOPB signals.

[0100] When STOPB signal is active all the above functionality isfulfilled with reversed roles of STOPB and PCBA versus STOPA and PCBB.

[0101] High resolution extension of phase measurements is explainedbelow.

[0102] The high resolution extension enhances phase detection resolutionto a single inverter delay i.e. by ˜10times compared with conventionalmethods based on clock counting. The high resolution measurement isimplemented in the HRPD Config.1, by using the phase capture register(PCR) to measure a positioning of the last rising edge of the secondsignal frame fr_(S2) versus the f_(F1) clock waveform

[0103] The phase capture register captures a state of outputs ofmultiple serially connected gates which the first signal clock f_(F1) iscontinuously propagated through, at the leading edge of the secondsignal frame fr_(S2).

[0104] PCR decoders are used in the high resolution extension, and theyare defined below.

[0105] The last rise decoder (LRD) provides binary encoded position off_(F1) rising edge, which has been captured at the most right locationof the PCR.

[0106] The cycle length decoder (CLD) provides binary encoded lengths ofthe f_(F1) wave, which has been captured between these 2 falling or 2rising edges of the f_(F1) wave which occurred at the most rightlocations of the PCR.

[0107] Captured PCR content is decoded by the last rise decoder and thecycle lengths decoder. Contents of the LRD and the CLD are latertransferred to the phase processing unit PPU).

[0108] The above operations are controlled by a Detector Timing Circuit,which is shown in the FIG. 1.

[0109] Timing analysis of the detector timing circuit is shown in FIG. 2and is explained below.

[0110] The High Clock Region Flip-Flop (HCR_FF) is set to1, when f_(F1)rise encounters PCR(0) set to 1. The PCR(0) was set to 1, if an fr_(S2)rise encountered f_(F1)=high. Therefore the HCR_FF=1 signals, thatfr_(S2) rising edge occurred during the f_(F1)=high halfcycle.

[0111] The PCR(1) is set to 1, when an fr_(S2) rise encountersf_(F1)=low. Therefore the PCR(1)=1 signals, that fr_(S2) rising edgeoccurred during the f_(F1)=low halfcycle.

[0112] PRESTOP_FF is set to1, when f_(F1) fall encounters HCR_FF orPCR(1) set to 1.

[0113] STOP_FF is reversed, by any rising edge of the PRESTOP_FF. AnySTOP_FF switching causes a reversal of the PCBA/PCBB functions.

[0114] The whole PCR is reset by the signal PhaDet_RST. The PhaDet_RSTshall be generated during fr_(S2)=low halfcycle and after contents ofthe PCR decoders are read by the phase processing unit.

[0115] It shall be noticed that a first f_(F1) rise which occurs afterfr_(S2) rise, will encounter unchanged status of the STOP_FF. Thereforepresently active counter will be increased by 1 by the first f_(F1)rise, but it will be freezed when following f_(F1) fall will reverse theSTOP_FF before an arrival of the second f_(F1) rise.

[0116] However since STOP_FF reversal was similarly delayed duringprevious fr_(S2) measurement, presently active counter missed countingone f_(F1) rise at the beginning of the present measurement.

[0117] Therefore the counter content needs to be decreased by 1, inorder to represent a correct number of complete f_(F1) cycles whichoccurred between consecutive rising edges of the fr_(S2) frame.

[0118] Phase processing method combines the approximate phasemeasurement and the high resolution extension into an actual phasemeasurement of a frame signal.

[0119] The phase processing method uses additional terms which areexplained below.

[0120] Calculated by PPU, measured phase (MEA_PHA) represents the actualphase error between fr_(S2) versus the equivalent f_(F1) frame; andconsists of the listed below components.

[0121] LRD/CLD is a normalized value of a phase error between fr_(S2)rise versus last f_(F1) rise, as it has been read by the PPU from theLRD and CLD decoders.

[0122] Remaining phase error (REM_PHA) is calculated based on thepresent measurement results, but PPU stores and uses it to correct thenext measurement result. The REM_PHA represents a remainder of apresently captured fraction of the f_(F1) period, which needs to beadded to the next phase error measurement.

[0123] Subtracted N which is a nominal number of first signal clocks pera second signal frame; transforms the counted number of f_(F1) cyclesper fr_(S2) period, into an approximate phase error between the fr_(S2)versus the f_(F1).

[0124] While the LRD/CLD represents a normalized PCR captured extensionof the CNTR(15:0) captured phase, and is added to the present MEA_PHA:the remaining phase error between the fr_(S2) and the next f_(F1) riseamounts to (CLD-LRD)/CLD and it is stored as the REM_PHA, in order tomodify next measurement's MEA_PHA.

[0125] Therefore:

MEA_PHA=REM_PHA+CNTR−1+LRD/CLD−N, REM_PHA=(CLD−LRD)/CLD.

[0126] 2. HRPD Config.2 based on ring oscillator captured by frame edge

[0127] For the approximate phase measurements the HRPD Config.2 uses thesame circuits as the HRPD Config.1.

[0128] High resolution extension for the Config.2 has differences versusthe Config.1, which are shown in the FIG. 3 and are listed below:

[0129] instead of using the open ended delay line as a first clocksignal propagation circuit, the ring oscillator which generates f_(F1)clock in the PLLxL Freq. Multiplier is used as said propagation circuit;

[0130] the cycle lengths decoder CLD is eliminated , because a number ofactive gates in the ring oscillator is known.

[0131] The phase capture register captures the state of outputs ofmultiple serially connected gates which form the ring oscillator whichthe first signal clock f_(F1) is continuously propagated through, at theleading edge of the second signal frame fr_(S2).

[0132] Since the ring oscillator gates must use lowered power supply, inorder to allow their delays controllability in the PLL configuration:phase detection resolution will be slightly lower for the Config.2versus the Config.1, but it still shall be significantly better whencompared with conventional methods limited to clock counting.

[0133] The detector timing circuit and the timing analysis are the samefor the Config.2 as for the Config.1 (see FIG. 1 and FIG. 2).

[0134] The only difference between a phase processing method of theConfig.2 versus the Config.1 is: that since ring gates number (RGN) isalways known, the Config.2 does not need to use the cycle lengthsdecoder and the CLD can be replaced by a ring gates number (RGN) in theequations calculating the MEA_PHA and the REM_PHA.

[0135] Therefore:

MEA_PHA=REM_PHA+CNTR−1+LRD/RGN−N, REM_PHA=(RGN−LRD)/RGN.

[0136] 3. HRPD Config.3 based on clock signal captured by frame delayline edges.

[0137] For the approximate phase measurements the HRPD Config.3 uses thesame circuits as the HRPD Config.1.

[0138] High resolution extension for the Config.3 has differences versusthe Config.1, which are shown in the FIG. 4 and are listed below:

[0139] instead of propagating the f_(F1) clock through a delay line, thesecond signal frame is propagated through the delay line, and outputs ofthe delay line gates are used to capture the f_(F1) clock incorresponding bits of the phase capture register (PCR);

[0140] the first rise decoder (FRD) is used in the Config.3 instead ofthe last rise decoder (LRD) from the Config.1, since the PCR contentrepresents f_(F1) waveform occurring after a rising edge of the fr_(S2)frame;

[0141] a new bit PCR(−1) is added to the PCR, in order to captureinverted f_(F1) value which was captured in the PCR(1) bit for theConfig.1.

[0142] Since non inverting gates must be used in the delay line,resolution is reduced compared with the Config.1, but still issignificantly better than with conventional methods.

[0143] For the detector timing circuits, the HRPD Config.3 uses similarsolutions as the HRPD Config.1: with the exception of using the signalPCR(−1) (see FIG. 5), instead of the signal PCR(1) (see FIG. 1) toenable activation of the PRESTOP_FF by the first falling edge of thef_(F1).

[0144] The timing analysis is very similar for the Config.3 (see FIG. 6)as for the Config.1 (see FIG. 2). The differencies are caused by thefact that for the Config.3 parts of waveforms which occur after therising edges of the frame signal are captured, and therefore thecaptured waveforms are shown on the right sides of the arrows indicatingappearances of the frame rising edges.

[0145] Phase processing method for the Config.3 is explained below.

[0146] Since for the Config.3, the PCR and its decoders represent a partof a waveform which occurs after a frame rising edge:

[0147] a content of the FRD divided by the CLD, represents a REM_PHAvalue which shall be added to the next measurement,

[0148] a fraction of the f_(F1) cycle which shall be added to thepresent measurement amounts to:

1−FRD/CLD=(CLD−FRD)/CLD.

[0149] Therefore:

MEA_PHA=REM_PHA+CNTR−1+(CLD−FRD)/CLD−N, REM_PHA=FRD/CLD.

[0150] 4. HRPD Config.4 based on frame delay line captured by clocksignal.

[0151] For the approximate phase measurements the HRPD Config.4 uses thesame circuits as the HRPD Config.1.

[0152] High resolution extension for the Config.4 has differences versusthe Config.1, which are shown in the FIG. 7 and are explained below.

[0153] Instead of propagating the f_(F1) clock through a delay line, thesecond signal frame is propagated through the delay line, and theoutputs of the delay line gates are captured after any rising edge ofthe second signal frame:

[0154] the first f_(F1) clock captures the frame delay line in the frontphase capture register (FPCR);

[0155] the second f_(F1) clock captures the frame delay line in the endphase capture register (EPCR).

[0156] A bit FPCR(−1) is used in the FPCR for capturing present value ofthe second signal frame fr_(S2) by the falling edge of the first signalclock f_(F1).

[0157] The last frame decoder (LFD) provides a binary encoded positionof the fr_(S2) rising edge versus the first following f_(F1) rising,which has been captured on the right side of the FPCR.

[0158] The cycle length decoder (CLD) provides a binary encoded lengthsof the f_(F1) wave which is calculated as a difference between a numberof gate delays captured in the EPCR versus a number of gate delayscaptured in the FPCR.

[0159] Detector Timing Circuit for the Config.4 has differences versusthe Config.1, which are shown in the FIG. 8 and are explained below.

[0160] FPCR(−1) is used to activate the HCR_FF which enables activationof the PRESTOP_FF, if an fr_(S2) rise occurred during f_(F1)=highcondition.

[0161] FPCR(0) is used directly to enable activation of the PRESTOP_FF,if an fr_(S2) rise occurred during f_(F1)=low condition.

[0162] An inverted PRESTOP_FF is used as active low STOPFN signal: inorder to preserve the frame delay line captured in the FPCR by the firstf_(F1) clock after a rising edge of fr_(S2). Normally all the risingedges of the f_(F1) clock keep capturing the frame delay line in theFPCR, until the capturing is inhibited by STOPFN=low. Since STOPFN=lowis generated between the first and the second f_(F1) rise after therising edge of fr_(S2), the final content of the FPCR is the delay linecaptured by the first f_(F1) rise.

[0163] Similarly an active low STOPEN signal is generated between thesecond and the third f_(F1) rise after the rising edge of fr_(S2). SinceSTOPEN=low inhibits farther capturing of the frame delay line in theEPCR, the final content of the EPCR is the delay line captured by thesecond f_(F1) rise.

[0164] Timing analysis for the Config.4 is shown in the FIG. 9.

[0165] The timing diagrams show both capture events: the delay linecapturing by the first f_(F1) rise, and the delay line capturing by thesecond f_(F1) rise.

[0166] The FPCR(−1) is activated before the FPCR(0): if fr_(S2) riseoccurs during f_(F1)=high condition and is captured by f_(F1) fall.Similarly the FPCR(0) is activated before the FPCR(−1): if fr_(S2) riseoccurs during f_(F1)=low condition and is captured by f_(F1) rise.

[0167] The STOPFN is shown to be activated as STOPFN=low by the f_(F1)fall after the first f_(F1) rise. Similarly the STOPEN is shown to beactivated as STOPEN=low by the f_(F1) fall after the second f_(F1) rise.

[0168] Phase processing method for the Config.4 is defined below.

[0169] LFD/CLD is a normalized value of a phase error between an fr_(S2)rise versus the first f_(F1) rise, as it has been read by PPU from theLFD and CLD decoders.

[0170] The content of the LFD divided by the CLD, represents a REM_PHAvalue which shall be added to the next measurement.

[0171] A fraction of the f_(F1) cycle which shall be added to thepresent measurement amounts to:

1−LFD/CLD=(CLD−LFD)/CLD.

[0172] Therefore:

MEA_PHA=REM_PHA+CNTR−1+(CLD−LFD)/CLD−N, REM_PHA=LFD/CLD.

[0173] 5. HRPD Config.5 based on frame captured by clock delay line.

[0174] For the approximate phase measurements the HRPD Config.5; usesthe same circuits as the HRPD Config.1.

[0175] High resolution extension for the Config.5 has differences versusthe Config.1, which are shown in FIG. 10 and are explained below.

[0176] The Config.5 implements said capture synchronization method:

[0177] by using the gates from G0 to GR to prevent the delay lineoutputs from capturing fr_(S2)=high into any PCR bit whenever the nextPCR bit has been set to 1 before;

[0178] by using the delayed phase capture register (DPCR) to provide PCRcontent which is delayed by f_(F1) halfcycle, in order to assuresufficient pulse duration for PCR input clocks.

[0179] For some integrated circuit technologies, PCR flip-flopspropagation delays may be sufficient to provide said required pulseduration. Therefore for such technologies the DPCR is not needed, sincean output of the next PCR bit can be connected directly to an inverterwhich prevents delay line output from passing through the gate connectedto the clock input of the current PCR bit.

[0180] The outputs of the delay line gates which the f_(F1) clock ispropagated through, keep capturing 0s in the PCR for as long as thesecond signal frame remains low.

[0181] When a rising edge of the fr_(S2) appears (see also FIG. 12):

[0182] the fr_(S2) rise is captured in the PCR simultaneously by tworising edges of the delay line outputs, which are separated by a numberof delay gates which corresponds to f_(F1) cycle;

[0183] the two rising edges keep propagating along the delay line andkeep capturing fr_(S2)=high in consecutive PCR bits for as long asencountered PCR bits have proceeding bits not set to 1;

[0184] in addition to said two rising edges, a third rising f_(F1) edgeenters the delay line from an f_(F1) source and will keep propagatingand capturing fr_(S2)=high until a bit is encountered which is proceededby a set to 1 bit.

[0185] Therefore:

[0186] the first delay line rising edge will set all the bits startingfrom its fr_(S2) detection bit down to the end of PCR;

[0187] the second delay line rising edge will set all the bits startingfrom its fr_(S2) detection bit until it encounters the bit which followsthe fr_(S2) detection bit of the first line rising edge;

[0188] the third delay line rising edge will set all the bits startingfrom the delay line entry until it encounters the bit which follows thefr_(S2) detection bit of the second line rising edge.

[0189] A bit PCR(−1) is used in the PCR for capturing present value ofthe second signal frame fr_(S2), by the falling edge of the first signalclock f_(F1).

[0190] First frame decoder (FFD) provides binary encoded position of thefr_(S2) rising edge versus the last proceeding f_(F1) rising which hasbeen captured on the left side of the PCR as the fr_(S2) detection bitof the second line rising edge.

[0191] Cycle length decoder (CLD) provides binary encoded lengths of thef_(F1) wave, which is calculated as a number of gate delays between: thefr_(S2) detection bit of the first line rising edge, and the fr_(S2)detection bit of the second line rising edge.

[0192] Since non inverting gates must be used in the delay line, theresolution is reduced compared with the Config.1, but still issignificantly better than with conventional methods.

[0193] Detector Timing Circuit for the Config.5 has differences versusthe Config.1, which are shown in the FIG. 11 and are explained below.

[0194] PCR(−1) is used to activate the HCR_FF which enables PRESTOP_FFactivation, if an fr_(S2) rise occurred during f_(F1)=high condition.

[0195] PCR(0) directly enables PRESTOP_FF activation, , if an fr_(S2)rise occurred during f_(F1)=low condition.

[0196] Phase processing method for the Config.5 is explained below.

[0197] FFD/CLD is a normalized value of a phase error between an fr_(S2)rise versus the last f_(F1) rise, as it has been read by the PPU fromthe FFD and the CLD decoders.

[0198] The content of the FFD divided by the CLD shall be added to thepresent phase measurement.

[0199] A fraction of the f_(F1) cycle which shall be added to the nextmeasurement amounts to:

1−FFD/CLD=(CLD−FFD)/CLD.

[0200] Therefore:

MEA_PHA=REM_PHA+CNTR−1+FFD/CLD−N, REM_PHA=(CLD−FFD)/CLD.

[0201] 6. HRPD Config.6 based on frame captured by ring oscillator.

[0202] For the approximate phase measurements, the HRPD Config.6 usesthe same circuits as the HRPD Config.5.

[0203] High resolution extension for the Config.6 has differences versusthe Config.5, which are shown in the FIG. 13 and FIG. 14 and areexplained below.

[0204] Instead of the open ended delay line, the outputs of the ringoscillator which is phase locked to a stable clock, are used to capturea rise of the fr_(S2) signal in the PCR.

[0205] Since the number of ring oscillator gates and the f_(F1) clockperiod are known, a calibration of the gates propagation delays is notneeded for the HRPD Config.6, and the CLD is not needed as well.

[0206] Since the calibration is not needed, and the oscillator gatesdelays cover all the f_(F1) clock period; the PCR can be much shorter,as it needs to cover only one f_(F1) clock period.

[0207] The Config.6 uses PLLxL Freq. Multiplier to provide the ringoscillator which is phase locked to a stable reference clock. Thereforering oscillator gates are the serially connected gates which the f_(F1)is propagated through, and are used to capture a rise of the secondsignal frame. The ring oscillator gates must use lower power supply inorder to allow their delays controllability in the PLL configuration.

[0208] Therefore, resolution is slightly reduced compared with theConfig.5, but still is significantly better than with conventionalmethods.

[0209] The detector timing circuit is the same for the Config.6 as forthe Config.5.

[0210] The timing analysis is very similar for the Config.6 as for theConfig.5. The only difference is that the PCR content is much shorter,since only one f_(F1) clock period needs to be captured.

[0211] The only difference between the phase processing method of theConfig.6 versus the Config.5 is: that since ring gates number (RGN) isalways known, the Config.6 does not need to use the cycle lengthsdecoder and the CLD can be replaced by the RGN in the equationscalculating the MEA_PHA and the REM_PHA.

[0212] Therefore:

MEA_PHA=REM_PHA+CNTR−1+FFD/RGN−N REM_PHA=(RGN−FFD)/RGN

[0213] While the invention has been described with reference toparticular example embodiments, further modifications and improvementswhich will occur to those skilled in the art, may be made within thepurview of the appended claims, without departing from the scope of theinvention in its broader aspect:

[0214] Numerous modification and variations of the present invention arepossible in light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims, the inventionmay be practiced otherwise than as specifically described herein.

What is claimed is:
 1. A digital phase detector, wherein the digitalphase detector comprises: a frame measurement configuration for countingthe first signal clock during every frame of a second signal, and forbuffering the counted value until it is read by a phase processing unit.2. A digital phase detector as claimed in claim 1, wherein: a nominalnumber of first signal clocks which corresponds to a zero phase skewbetween the first signal and the second signal, is subtracted from thecounted number of the first signal clocks, in order to calculate anapproximate frame skew.
 3. A digital phase detector as claimed in claim1, wherein: a number of first signal clocks which equals to zero minusthe nominal number of first signal clocks, is preset in a counter of thefirst signal clock before the first clock counting for every second,signal frame.
 4. A digital phase detector as claimed in claim 1, furthercomprising: a phase capture register for capturing a state of outputs ofserially connected gates which the first signal clock is propagatedthrough, at the leading edge of the second signal frame.
 5. A digitalphase detector as claimed in claim 1, further comprising: a phasecapture register for capturing a rise of the second signal frame bymultiple outputs of serially connected gates which the first signalclock is propagated through.
 6. A digital phase detector as claimed inclaim 1, further comprising: a phase capture register for capturing astate of outputs of serially connected gates which the second signalframe is propagated through, by the leading edge of the first signalclock.
 7. A digital phase detector as claimed in claim 1, furthercomprising: a phase capture register for capturing a rise of the firstsignal clock, by multiple outputs of serially connected gates which thesecond signal frame is propagated through
 8. A digital phase detector asclaimed in claim 4 or in claim 5 or in claim 6 or in claim 7, whereinthe digital phase detector comprises: an open ended line of seriallyconnected components which are used as the serially connected gates. 9.A digital phase detector as claimed in claim 4 or in claim 5 or in claim6 or in claim 7, wherein the digital phase detector comprises: a ringoscillator which gates are used as the serially connected gates.
 10. Adigital phase detector as claimed in claim 4 or in claim 5 or in claim 6or in claim 7, wherein the digital phase detector comprises: a delaylocked loop which gates are used as the serially connected gates.
 11. Adigital phase detector as claimed in claim 1, the digital phase detectorcomprising: a first phase counter buffer for counting first signalclocks during every odd cycle of the second signal frame, and forbuffering the counted clocks number during every following even cycle ofthe second signal frame; a second phase counter buffer for countingfirst signal clocks during every even cycle of the second signal frame,and for buffering the counted clocks number during every following oddcycle of the second frame.
 12. A digital phase detector as claimed inclaim 11, wherein the digital phase detector comprises: a detectortiming circuit for controlling the counting and the buffering functionsof the first and the second phase counter buffers.
 13. A digital phasedetector as claimed in claim 11, wherein said detector timing circuitfurther comprises: detection of a beginning of a cycle of the secondsignal frame; switching the counter buffers into the counting andbuffering operations; requesting the phase processing unit to read thebuffered count numbers;
 14. A digital phase detector as claimed in claim11, wherein: the first counter buffer is reset after its content is readby a phase processing unit; the second counter buffer is reset after itscontent is read by the phase processing unit.
 15. A digital phasedetector as claimed in claim 14, wherein: the nominal number of firstsignal clocks which corresponds to a zero phase skew between the firstsignal and the second signal, is subtracted by the phase processing unitfrom the read content of any counter buffer.
 16. A digital phasedetector as claimed in claim 11, wherein: the first counter buffer ispreset to zero minus the nominal number of first signal clocks, afterits content is read by the phase processing unit; the second counterbuffer is preset to zero minus the nominal number of first signalclocks, after its content is read by the phase processing unit.
 17. Adigital phase detector as claimed in claim 1, wherein: said first clockcounting is enabled by opening a logical gate which controls anapplication of the first clock to counter's clocking input; said firstclock counting is disabled by closing a logical gate which controls anapplication of the first clock to counter's clocking input.
 18. Adigital phase detector as claimed in claim 4 or in claim 5 or in claim 6or in claim 7, wherein: a content of the phase capture register is usedto calculate a phase skew difference between the last rise of the firstsignal clock and the beginning of a new second signal frame; a contentof the phase capture register is used to calculate a remaining phaseskew between the beginning of a new second signal frame and the firstrise of the first signal clock.
 19. A digital phase detector as claimedin claim 18, wherein: the phase skew difference is added to the presentmeasurement of a phase skew between the first signal and the secondsignal, wherein the present measurement applies to the present frameperiod of the second signal; the remaining phase skew is added to thenext measurement of a phase skew between the first signal and the secondsignal, wherein the next measurement applies to the next frame period ofthe second signal.
 20. A digital phase detector as claimed in claim 18,wherein: the remaining phase skew is calculated as equal to the firstsignal clock period minus the phase skew difference.
 21. A digital phasedetector as claimed in claim 18, wherein: a content of the phase captureregister is used to upgrade the counted number of first signal clocks toan actual number of first signal clocks which really occurred during thesecond signal frame.
 22. A digital phase detector as claimed in claim 8,wherein the digital phase detector comprises a calibration method ofgates propagation delays, wherein: a number of the serially connectedgates which represents a number of half cycle times of the first signalclock, is captured in the phase capture register; the number of halfcycle times of the first signal clock, is divided by the capturednumber.
 23. A digital phase detector as claimed in claim 22, wherein thecalibration method comprises: a statistical averaging of a result of thecalibration, in order to eliminate most of a granularity error caused bycapturing of an integer and to reduce an error caused by a power supplyripple.
 24. A digital phase detector as claimed in claim 23, wherein thecalibration method further comprises: assigning higher weights for thecaptured number of gates, if the captured number is provided by seriallyconnected gates which are located at the front of the delay line; usingthe weighted cycle gate numbers for the statistical averaging of thecalibration result.
 25. A digital phase detector as claimed in claim 4or in claim 5 or in claim 6 or in claim 7, wherein the digital phasedetector comprises: a first phase counter buffer for counting firstsignal clocks during every odd cycle of the second signal frame, and forbuffering the counted clocks number during every following even cycle ofthe second signal frame; a second phase counter buffer for countingfirst signal clocks during every even cycle of the second signal frame,and for buffering the counted clocks number during every following oddcycle of the second frame. a detector timing circuit for switching thecounting and the buffering functions of the first and the second phasecounter buffer.
 26. A digital phase detector as claimed in claim 25,wherein: the switching performed by the detector timing circuits isdriven by the first signal clock and is conditioned by a content of thephase capture register.
 27. A digital phase detector as claimed in claim25, wherein: the phase capture register and some of the flip-flops ofthe detector timing control, are reset outside of a close time rangewhich surrounds a rising edge of every second signal frame.
 28. Adigital phase detector as claimed in claim 25, wherein: if a rising edgeof the second signal frame encounters a high level of the first signalclock, the second falling edge of the first signal clock will reversethe counting and the buffering functions of the first and the secondphase counter buffer; if a rising edge of the second signal frameencounters a low level of the first signal clock, the first falling edgeof the first signal clock will reverse the counting and the bufferingfunctions of the first and the second phase counter buffer.
 29. Adigital phase detector as claimed in claim 25, wherein the detectortiming circuit comprises a function switching flip-flop, wherein: thefunction switching flip-flop switched to 1, inhibits counting in thefirst counter buffer and enables counting in the second counter buffer;the function switching flip-flop switched to 0, inhibits counting in thesecond counter buffer and enables counting in the first counter buffer.30. A digital phase detector as claimed in claim 11, wherein the digitalphase detector further comprises: a detector timing circuit forswitching the counting and the buffering functions of the first and thesecond phase counter buffer.
 31. A digital phase detector as claimed inclaim 30, wherein the detector timing circuit further comprises afunction switching flip-flop, wherein: the function switching flip-flopswitched to 1, inhibits counting in the first counter buffer and enablescounting in the second counter buffer; the function switching flip-flopswitched to 0, inhibits counting in the second counter buffer andenables counting in the first counter buffer.
 32. A digital phasedetector as claimed in claim 31, wherein the digital phase detectorfurther comprises: a phase capture register for capturing a state ofoutputs of serially connected gates which the first signal clock ispropagated through, at the leading edge of the second signal frame; anopen ended line of serially connected components which are used as theserially connected gates.
 33. A digital phase detector as claimed inclaim 31, wherein the digital phase detector further comprises: a phasecapture register for capturing a state of outputs of serially connectedgates which the first signal clock is propagated through, at the leadingedge of the second signal frame; a ring oscillator which gates are usedas the serially connected gates.
 34. A digital phase detector as claimedin claim 31, wherein the digital phase detector further comprises: aphase capture register for capturing a rise of the first signal clock,by multiple outputs of serially connected gates which the second signalframe is propagated through; an open ended line of serially connectedcomponents which are used as the serially connected gates.
 35. A digitalphase detector as claimed in claim 31, wherein the digital phasedetector further comprises: a phase capture register for capturing astate of outputs of serially connected gates which the second signalframe is propagated through, by the leading edge of the first signalclock. an open ended line of serially connected components which areused as the serially connected gates.
 36. A digital phase detector asclaimed in claim 31, wherein the digital phase detector furthercomprises: a phase capture register for capturing a rise of the secondsignal frame by multiple outputs of serially connected gates which thefirst signal clock is propagated through; an open ended line of seriallyconnected components which are used as the serially connected gates. 37.A digital phase detector as claimed in claim 31, wherein the digitalphase detector further comprises: a phase capture register for capturinga rise of the second signal frame by multiple outputs of seriallyconnected gates which the first signal clock is propagated through, aring oscillator which gates are used as the serially connected gates.38. A digital phase detector as claimed in claim 32 or in claim 33 or inclaim 34 or in claim 35 or in claim 36 or in claim 37, wherein: anapproximate frame skew is calculated as equal to the counted number ofclock cycles minus the nominal number of first signal clocks; a contentof the phase capture register is used to calculate a phase skewdifference between the last rise of the first signal clock and thebeginning of a new second signal frame; a content of the phase captureregister is used to calculate a remaining phase skew between thebeginning of a new second signal frame and the first rise of the firstsignal clock; a high resolution extension is calculated by adding theremaining phase skew of the previous measurement to the phase skewdifference of the present measurement; a high resolution frame skew iscalculated by adding the approximate frame skew to the high resolutionextension.
 39. A digital phase detector as claimed in claim 32 or inclaim33, wherein: bit 0 of the phase capture register is set to 1, if arising edge of the second signal frame encounters a high level of thefirst signal clock; bit 1 of the phase capture register is set to 1, ifa rising edge of the second signal frame encounters a low level of thefirst signal clock; if the bit 0 is set to 1, it enables a secondfalling edge of the first signal clock to reverse the function switchingflip-flop; if the bit 1 is set to 1, it enables a first falling edge ofthe first signal clock to reverse the function switching flip-flop. 40.A digital phase detector as claimed in claim 34, wherein: bit 0 of thephase capture register is set to 1, if a rising edge of the secondsignal fame encounters a high level of the first signal clock; bit−1 ofthe phase capture register is set to 1, if a rising edge of the secondsignal frame encounters a low level of the first signal clock; if thebit 0 is set to 1, it enables a second falling edge of the first signalclock to reverse the function switching flip-flop; if the bit−1 is setto 1, it enables a first falling edge of the first signal clock toreverse the function switching flip-flop.
 41. A digital phase detectoras claimed in claim 35 or in claim36 or in claim 37, wherein: bit−1 ofthe phase capture register is set to 1, if a falling edge of the firstsignal clock encounters a high level of the second signal frame before arising edge of the first signal clock does; bit 0 of the phase captureregister is set to 1, if a rising edge of the first signal clockencounters a high level of the second signal frame before a falling edgeof the first signal clock does; if the bit−1 is set to 1, it enables asecond falling edge of the first signal clock to reverse the functionswitching flip-flop; if the bit 0 is set to 1, it enables a firstfalling edge of the first signal clock to reverse the function switchingflip-flop.